1. Field of the Invention
This invention relates generally to methods of interconnecting multiple chips to form a hybrid device, and more particularly to a self-aligning hybridization method which is well-suited for small pixel pitch applications.
2. Description of the Related Art
A “hybrid” device typically contain two or more separately-fabricated integrated circuits (ICs or “chips”) within a common package. Generally, the separate chips must be interconnected in some fashion to provide a functional device. The techniques used to facilitate the interconnection is commonly referred to “hybridization”.
The chips within a given hybrid are often in a ‘stacked’ arrangement, with an interconnection means employed between the chips to connect contact pads on the top of the lower chip with corresponding contact pads on the bottom of the upper chip. One common hybridization technique uses indium bumps deposited on both chips' mating surfaces. The chips are then brought into contact with each other such that the bumps are pressed together, causing them to deform and bond together. However, there is no means of ensuring the alignment of the respective indium bumps; in fact, in practice, the bumps are often out of alignment and slip off each other.
Another problem with this conventional hybridization technique is ‘run-out’. An indium bump is typically around 10 μm in diameter before being deformed as described above, with a target compression of about 50%. When pressed together, the diameter of the bump(s) expands, which is known as run-out. However, the indium can deform too much or in unpredictable directions, which can lead to shorts when adjacent contacts are in close proximity to each other. For example, a hybrid detector device typically includes a first chip containing a large array of pixels, each of which must interface with a second, control IC. The distance between the centerlines of adjacent pixels is referred to as ‘pixel pitch’. As pixel pitch drops below 10 μm, both indium run-out and hybridization alignment can make existing methods of interconnecting the chips unsuitable.
One approach to mitigating these problems is offered by DRS Technologies, who describe a fine-pitch bump technology in which one chip mating surface has metal pads in respective recesses, and the other mating surface has indium bumps which are intended to contact the metal pads when the chips are brought together. However, there is still no means of ensuring the alignment of the indium bumps with the metal pads.